BeenLi

leo jagten

BeenLi

do what you can

Xianning
Joined November 2018

xv6-riscv

Xv6 for RISC-V

CUpdated 1/17/2025

linux

Linux kernel source tree

CUpdated 11/19/2024

CXL-DMSim

CXL-DMSim: A Full-System CXL Disaggregated Memory Simulator Based on gem5

Updated 10/29/2024

wujian100_open

IC design and development should be faster,simpler and more reliable

VerilogUpdated 6/6/2024

openc910

OpenXuantie - OpenC910 Core

VerilogUpdated 6/6/2024