AHB2
AMBA AHB 2.0 VIP in SystemVerilog UVM
SystemVerilogUpdated 3/30/2021
molokai
Molokai color scheme for Vim
Updated 3/10/2021
uvmprimer
Contains the code examples from The UVM Primer Book sorted by chapters.
SystemVerilogUpdated 1/23/2021
ibex
Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.
Updated 6/2/2020
scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
SystemVerilogUpdated 5/28/2020