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Open Issues

Problems with Vivado simulator

#53Opened 4/29/20244 commentsby Nick1296

Support Veridi Protocol/Performance Analyzer

#45Opened 8/16/20220 commentsby taichi-ishitani

Support Vivado simulator

#32Opened 5/8/20226 commentsby taichi-ishitani

Error when elab with Vivado

#28Opened 12/30/20209 commentsby aignacio

uvm reg adapter supports AXI4 access

#17Opened 7/24/20200 commentsby taichi-ishitani

Add ability to generate non-byte access by reg API

#16Opened 7/23/20205 commentsby klevin92

Open Source Verilog Simulator with This

#13Opened 1/4/20201 commentsby coder-humbitious

fixed and wrapping burst support

#10Opened 7/9/20190 commentsby taichi-ishitani

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